The present invention relates to an arrangement of a circuit for resetting an internal state of a main circuit at the rise time of a power supply voltage.
A conventional power supply circuit having a reset circuit of this type has an arrangement shown in, e.g., FIG. 4. A reset circuit 2 is connected to an integrated circuit (IC) 1 as a main circuit. A voltage from a battery 3 is stored in a capacitor C1 so as to supply a stable power supply voltage to the IC 1.
When a switch S is closed, the reset circuit 2 receives a power supply voltage and supplies a reset signal to the IC 1, thus resetting the internal state thereof. FIGS. 5 and 6 show changes in voltage applied to the IC 1 when the switch S is opened and closed.
FIG. 5 shows changes in terminal voltage when the switch S is closed. More specifically, when the switch S is closed, and a DC voltage V.sub.CC is applied from the battery 3 to the IC 1 and the reset circuit 2 at time t=0, the voltage of a power supply input terminal 4 of the IC 1 substantially reaches V.sub.CC at t=0, provided that the capacitance of the input terminal 4 is negligibly small, as indicated by a curve 4a in FIG. 5.
Assume that a sufficient period of time has elapsed at time t&lt;0 after the switch S is opened, charges in the capacitor C1 and a capacitor C2 are discharged through resistors R1 and R2, and no charges are left in the capacitor C2. In this case, when the switch S is closed, a voltage is applied to a reset input terminal 5 in accordance with a time constant determined by the resistor R1 and the capacitor C2, as indicated by a curve 5a in FIG. 5. Providing that the resistor R1 has a resistance r.sub.1 (.OMEGA.) and the capacitor C2 has a capacitance c.sub.2 (F), a time constant .tau..sub.1 is given by .tau..sub.1 =r.sub.1.c.sub.2 (S). Referring to FIG. 4, reference numeral 6 denotes a GND terminal.
If the switch S is closed, and a power supply voltage is applied to the IC 1 in this manner, the voltage V.sub.cc is applied to the power supply voltage input terminal 4 when time t is close to 0. At the same time, a voltage close to 0 V is applied to the reset input terminal 5, and the voltage of the reset input terminal 5 reaches V.sub.cc with the lapse of time. Subsequently, the internal state of the IC 1 is reset to 0 V, i.e., "Low" logic level. More specifically, the IC 1 is reset by a reset signal having a voltage close to 0 V, which is applied to the reset input terminal 5. The reset state of the IC 1 is canceled when the voltage of the reset input terminal 5 is increased after the reset operation.
FIG. 6 shows changes in terminal voltages when the switch S is opened. When the switch S is opened (t =t.sub.a), and no power supply voltage is applied to the IC 1, the voltage of the reset input terminal 5 is decreased as indicated by a curve 5b in FIG. 6, provided that the capacitor C1 can be neglected, as indicated by the following equation: ##EQU1##
In practice, however, a capacitor having a large capacitance is generally used as the capacitor C1 in order to stabilize a power supply voltage, and hence c.sub.1 &lt;c.sub.2 is established. If, therefore, the current consumption of the IC 1 is small, the voltage of the reset input terminal 5 exhibits changes indicated by a curve 5c in FIG. 6, due to the following time constant as a dominant factor: ##EQU2##
Note that a portable radio transceiver does not have the switch S, and the reset circuit 2 is operated upon mounting and dismounting of the battery 3.
The following problem is posed in the above-described reset circuit 2. When the switch S is opened and is subsequently closed again before the voltage of the reset input terminal 5 is sufficiently decreased, the IC 1 cannot be reset in spite of the fact that the power supply voltage applied to the IC 1 is decreased once.
In order to solve such a problem, the time constant .tau..sub.2 needs to be made small, and r.sub.2 and c.sub.1 need to be made small to minimize the time constant .tau..sub.3 if the current consumption of the IC 1 is small. However, the capacitance c.sub.1 of the capacitor C1 needs to be relatively large to stabilize a power supply voltage and hence cannot be set to be small. In addition, if the resistor R2 (r.sub.2) is made small, a current corresponding to the decrease in r.sub.2 undesirably flows constantly.
Since a decrease in the time constant .tau..sub.3 is limited in this manner, it is difficult to prevent variations in power supply voltage in a decreased state, which are caused upon, e.g., quick switching of power supplies, from influencing a reset operation.